Includes

TestBencher Pro
VeriLogger Pro
Waveformer Pro
DataSheet Pro
TimingDiagrammer Pro


1.VHDL, Verilog, and TestBuilder Graphical Test Bench Generation
TestBencher Pro is a graphical test bench generator that dramatically reduces the time required to create and maintain test benches. One of the most time consuming tasks for users of HDL languages is coding test benches to verify the operation of their design. In his book “Writing Testbenches,” Janick Bergeron estimates that 70% of design time is spent verifying HDL code models and that the test bench makes up 80% of the total HDL code generated during product development.

2.High-performance compiled-code Verilog 2001 simulator
VeriLogger Extreme is a completely new, high-performance compiled-code Verilog 2001 simulator that significantly reduces simulation debug time. VeriLogger Extreme offers fast simulation of both RTL and gate-level simulations with SDF timing information. VeriLogger Extreme supports design libraries and design flows for all major ASIC and FPGA vendors, including Actel, Altera, Atmel, LSI Logic, QuickLogic, and Xilinx.

3.WaveFormer Pro is a revolutionary new rapid-prototyping EDA tool that helps you design faster and with fewer mistakes.

WaveFormer Pro enables you to automatically determine critical paths, verify timing margins, adjust for reconvergent fanout effects, and perform “what if” analysis to determine optimum clock speed. WaveFormer Pro also lets you specify and analyze system timing and perform Boolean level simulation without the need for schematics or simulation models. When your timing diagram is complete, you can then generate digital stimuli for your favorite Verilog, VHDL, SPICE or gate-level simulator. WaveFormer Pro has the ability to import and annotate simulation and logic analyzer data, for publication quality design documentation.

4.DataSheet Pro provides the ultimate environment for documentation professionals working with multi-diagram projects.

Datasheet Pro’s project management features allow users to efficiently combine diagrams from multiple engineers into one project with uniform formatting. Using Object Linking and Embedding (OLE), users can embed timing diagrams into other publishing programs. These images can be edited at any time directly from the publishing program by double clicking on the image to launch DataSheet Pro with the selected timing diagram. Other features include style sheets, view support, web-ready image generation, analog waveform import and display, and support for the industry-standard Timing Diagram Markup Language (TDML) format. Documentation professionals will be able to receive timing diagrams produced by design engineers using any TDML-compatible product, such as WaveFormer Pro or Timing Diagrammer Pro, and embed them directly into publishing programs like FrameMaker and Word.

5.Timing Diagrammer Pro has everything that you expect in a timing diagram editor: a modeless drawing and editing environment; delays, setups, and holds for performing timing analysis; time markers; seven graphical waveform states; virtual and group buses; clocks with formulas; as well as a variety of ways to document your work. A great timing analysis tool at a great price, Timing Diagrammer Pro is a must-have for any engineer.


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